In an attempt to increase the performance and capacity of memory devices, a plurality of memory chips can be interconnected to form a memory module, such as a dynamic random access memory (DRAM), on a printed circuit board (PCB).
Such memory modules may be classified into single in-line memory modules (SIMMs), in which a plurality of memory chips are connected to one surface of a PCB, and dual in-line memory modules (DIMMs), in which a plurality of memory chips are connected to both surfaces of a PCB. An FBDIMM (fully buffered DIMM) is one type of DIMM that has been developed to allow high-operating speed and large memory capacity using a packet protocol. The FBDIMM includes an interface chip for converting a packet type serial interface into a DRAM interface. The interface chip is a unit that transforms a high-speed packet received from a host, such as a microprocessor, into a memory command, and provides an interface between a received signal and a transmitted signal. In general, the interface chip is referred to as an advanced memory buffer (AMB) chip.
FIG. 1 is a block diagram of a conventional semiconductor memory device 100 that is configured as a FBDIMM. Referring to FIG. 1, the semiconductor memory device 100 includes a controller 110, a first memory module 120, and a second memory module 130. The first memory module 120 is connected to an interface chip, e.g., a first AMB chip AMB_1, and a plurality of memory chips 121, 122, . . . , 128. Similarly, the second memory module 130 is connected to a second AMB chip AMB_2 and a plurality of memory chips 131, 132, . . . , 138. The controller 110 exchanges a signal, e.g., an address, a command, or data, with the first and second memory modules 120 and 130.
When the controller 110 transmits a signal related to the first memory module 120, the first AMB chip AMB_1 receives the signal and transmits it to a corresponding memory chip of the first memory module 120. If the controller 110 transmits a signal related to the second memory module 130, the first AMB chip AMB_1 receives the signal and transmits it to the AMB chip AMB_2. Then, the second AMB chip AMB_2 receives the signal and transmits it to a corresponding memory chip of the second memory module 130.
For example, in order to read data from the memory chip 123, the controller 110 transmits a read command for reading the data from the memory chip 123 to the first AMB chip AMB_1. The first AMB chip AMB_1 receives the read command and transmits it to the memory chip 123, and the memory chip 123 performs a read operation. The data read through the read operation is transmitted to the controller 110 via the first AMB chip AMB_1. In order to read data from the memory chip 136, the controller 110 transmits a read command for reading the data from the memory chip 136 to the first AMB chip AMB_1. Since the read command is not related to the first memory module 120, the first AMB chip AMB_1 delivers the read command to the second AMB chip AMB_2. Then, the second AMB chip AMB_2 receives the read command and transmits it to the memory chip 136, and the memory chip 136 performs a read operation. The data read through the read operation is transmitted to the controller 110 via the first AMB chip AMB_1 and the second AMB chip AMB_2. When a command or data is transmitted as described above, unidirectional signal transmission is performed between the controller 110 and the first AMB chip AMB_1 and between the first AMB chip AMB_1 and the second AMB chip AMB_2, and bidirectional signal transmission is performed between the first AMB chip AMB_1 and the memory chips 121, . . . , 128 and between the second AMB chip AMB_2 and the memory chips 131, . . . , 138.